sung_chul
New Contributor
3 years agoTransceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP
Hi-
"Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP" is an IP that receives 40-bit parallel input and outputs high-speed serial output
I read 40 bits from ROM and write it in parallel to 'Transceiver IP.'
i tested it.
1) ROM Data "10101010.....1010 (40bit)" It's OK!
But,
2) ROM data "00000....1111" (40bit) ← 20bit '0' & 20bit '1', It's not OK!
I used a differential probe..
The output is as follows
I want the same result as the red line.
I guess this has something to do with pre-emphasis.
Who knows how to adjust the options?
Thanks!