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Transceiver Native PHY clock and data width
Hi,
As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you,
Kshitij Goel
3 Replies
- Kshitij_Intel
Frequent Contributor
Hi,
It could be due to 8b/10b encoding. For 32bit, there will be 40bits and 62.5*40 = 2500.
Hope it clarifies now.
Thank you,
Kshitij Goel
- Kshitij_Intel
Frequent Contributor
Hi,
As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you,
Kshitij Goel
- MaCo
New Contributor
Hi Intel guys,
just a remark, I can't press the "Accept as solution" button using Firefox under Ubuntu 2020.2 LTS, got only an error message.