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MaCo's avatar
MaCo
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Transceiver Native PHY clock and data width

Hello, I configured the Transceiver Native PHY for a Cyclone V GX design to 2500 Mbps and enabled the simplified data interface so that I get a 32 bit data interface for tx and rx. The measured clocks...
Ethernet
  • Kshitij_Intel's avatar
    Kshitij_Intel
    2 years ago

    Hi,


    As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

    Thank you,

    Kshitij Goel


Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


It could be due to 8b/10b encoding. For 32bit, there will be 40bits and 62.5*40 = 2500.


Hope it clarifies now.


Thank you,

Kshitij Goel