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Altera_Forum
Honored Contributor
10 years ago --- Quote Start --- You must work with frame clock or bit clock of A/D converter. FPGA's clock and ADC's clock are asynchronous you will have wrong data reception. Regards, Andrei --- Quote End --- Thanks again, Andrei. I'll use bit clock as the the input clock of ALTLVDS_RX's internal PLL, and use frame clock to decide whether to pulse rx_channel_data_align or not. Regards, zhangfeng