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Altera_Forum
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11 years ago

to use altlvds,how I can use LVDS bit clock and LVDS frame clock of ADC at the same t

In my board, there are 5AGXFB3H4F40C5N and TI ADS5294. The ADS5294 is a 80-MSPS 8-Channel ADC,The digital data from each channel ADC is output over two wires of LVDS output lines depending on the ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

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Not necessarily, if you use the frame clock as PLL input clock and multiply it to half the bit rate. I implemented many different LVDS ADC interfaces this way, with 12, 14 and 16 bit width. The phase of the internal generated bit and frame clock can be adjusted for maximal sampling window margin.

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Thanks, FvM.

If I don't use the frame clock as PLL input clock, but use FPGA's clock as the PLL input clock, can I get the correct data from the A/D converter?

Best regards,

zhangfeng