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Altera_Forum
Honored Contributor
Honored Contributorto use altlvds,how I can use LVDS bit clock and LVDS frame clock of ADC at the same t
In my board, there are 5AGXFB3H4F40C5N and TI ADS5294. The ADS5294 is a 80-MSPS 8-Channel ADC,The digital data from each channel ADC is output over two wires of LVDS output lines depending on the ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- 1, When I choose internal PLL for altlvds_rx, do I need to connect lvds bit clock from A/D converter to the FPGA? --- Quote End --- Not necessarily, if you use the frame clock as PLL input clock and multiply it to half the bit rate. I implemented many different LVDS ADC interfaces this way, with 12, 14 and 16 bit width. The phase of the internal generated bit and frame clock can be adjusted for maximal sampling window margin.
