New Contributor
Super ContributorI would assume that the original design from the rocket board do not have timing violation. can you confirm that?
What you can do is try number 1 first and number 3 to see which causes the timing violation.
But, you should understand how does the timing behave in the FPGA and make the timing closure. Otherwise, you might ended up writing the wrong constrain and run the full compilation.
Make sure you go through the module https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html and all the follow on courses before you start looking on timing closure on your design. You will be understand why time quest reporting negative slack on your design.
New ContributorHi,
Thanks for the tips. We compiled the original design without any changes. It only had minimal timing violations, specifically on "Recovery" only, unlike when we compiled it to Gen-3 x8 which yielded more timing violations as was found on the sta.rpt file I attached previously. We also have tried the steps you mentioned. So far, we still have no clues to what causes the violations.
The GHRD in the link was compiled using Q15.1 and we are using 17.1. Could it be possible that different versions of Quartus will also yield different results?
I will go through the module you suggested. (thanks for this)
