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Jonni's avatar
Jonni
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7 years ago

Timing violations when configuring PCIe HIP @ Gen-3 x8 256bit

Hi Intel, We are having timing violations reported by TimeQuest when using PCIe HIP configured as Root Port @ Gen-3 x8 256bit using your downloadable GHRD (w/ pcie) files for Arria 10 SOC DevKit as ...
Jonni's avatar
Jonni
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7 years ago

Hi,

We got the ref design here:

https://rocketboards.org/foswiki/Projects/Arria10PCIeRootPortWithMSI

Exact link:

http://releases.rocketboards.org/release/2016.02/pcierd/hw/a10_pcie_soc_devkit.tar.gz

The changes we made were minimal:

  1. Set the PCIe HIP to Gen-3 x8 as it was compiled originally at Gen-2 x4 in Qsys (found in its "subsys".qsys file)
  2. Regenerated Qsys files (both subsys and top).
  3. Changed .qsf file to expose the pin-outs of the additional 4 xcvr ports both for RX and TX, following the same xcvr pin settings as the original.

The additional HW pin-outs were referenced to the GHRD schematic file of the PCIe Root Port XCVRs

.

Thanks!