Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Timing Violation for legacy DDR2 Controller

Hi There, I generated DDR2 SDRAM controller using mega wizard for memory frequency of 125 MHz and data width of 8. Timing analysis is failing because of violation in read data synchronization p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

All settings are same, except constraints, and I believe for different target device, it has to vary. The constraint setting page for StratixIIGX1152 is different from what you sent to me.