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Altera_Forum
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17 years ago

Timing Violation for legacy DDR2 Controller

Hi There, I generated DDR2 SDRAM controller using mega wizard for memory frequency of 125 MHz and data width of 8. Timing analysis is failing because of violation in read data synchronization p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I did not edit the "constraints" section in the Megawizard. I am not able to find the example where DDR2 SDRAM controller is used. Can you please tell me the exact path.