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Altera_Forum
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17 years ago

Timing Violation for legacy DDR2 Controller

Hi There, I generated DDR2 SDRAM controller using mega wizard for memory frequency of 125 MHz and data width of 8. Timing analysis is failing because of violation in read data synchronization p...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Did you run the TCL script generated by the megacore? This performs placement of various registers in the data path.

Jake