K_Crocker
Occasional Contributor
Occasional ContributorTiming for PLL clock PLL_RECONFIG~FMAX_CAP_FF
Each PLL instantiated in my design has a PLL_RECONFIG~FMAX_CAP_FF clock that isn't constrained. Can I constrain these clocks, and, if so, what frequency value should I use? TIA for your answer!
Hi Richard,
The design is quite large, so I can't share it. But to the point, the error is within the Reconfigurable PLL IP block. I think it has to do with the strange timing of the "phase_done" signal, which I believe I have accounted for after carefully reading the user guide. I was hoping that you might have some special knowledge from seeing this condition before.
So, that said, I think I'll false path or underconstrain the "clock" to get around the issue and close out this request. Thank you for your help.
