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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

Hi there, is there any updates on this issue?


  • SERMASWATHIKA's avatar
    SERMASWATHIKA
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    2 years ago

    Hi,

    i have checked the design with clk connected from inclk directly and compiled the design.

    But still timing violations are there.

    i have created another threat for ddr3_timing and sharing project archive with reports.

    based on the inputs from that thread, modified the project .

    Sharing the project with this