timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Just look into the screenshot that you provide, when I try to compile the design and load the PD, I see that you left your avalon pipeline bridge as dangling.

Any reason for that? You can actually connect this pipeline from your CPU.data master to Avalon_pipeline_bridge to TC timing to increase the pipeline for you to close the timing. I would suggest you download one of the example design in the NIOS II in the design store to see how the connection look like.

As you can see above, there are quite a lot of red module that prevent me to make modification of your design for timing closure. Can you let me know what are the setting that you use or the _hw.tcl script location for your custom module?