Forum Discussion

SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
2 years ago

timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
Memory
TingJiangT_Intel's avatar
TingJiangT_Intel
Icon for Contributor rankContributor
2 years ago

This data path is too long, and its logic level is high:

You created a loop here which has increased the data delay, please consider inserting pipeline registers into this path in your design to reduce the logic level.

SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
2 years ago

Hi,

Thanks for your response.

I just modified the qsys design for better timing performance so instead of ddr_pll clock , added pll ip to drive other rtl logic clock.

With that timing is improved. But still path has violation

The logic level is 4 only. These are listed for ddr3 ip library files. How to add pipeline register here?