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SERMASWATHIKA
Contributor
Contributortiming_error_for_pll_afi_clock_on_ddr3_ip_controller
Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
TingJiangT_IntelContributor
ContributorThis data path is too long, and its logic level is high:
You created a loop here which has increased the data delay, please consider inserting pipeline registers into this path in your design to reduce the logic level.
SERMASWATHIKAContributor
ContributorHi,
the critical path which you are showed in response is removed from timing violation as i added pll for managing clocks for rtl logic.
Now some other timing violations are there
these violations are within ddr3 library files. How to add pipeline register in this path?
