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SERMASWATHIKA
Contributor
Contributortiming_error_for_pll_afi_clock_on_ddr3_ip_controller
Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setti...
TingJiangT_IntelContributor
ContributorThis data path is too long, and its logic level is high:
You created a loop here which has increased the data delay, please consider inserting pipeline registers into this path in your design to reduce the logic level.
SERMASWATHIKAContributor
ContributorHi,
the critical path which you are showing is currently not available as i have added one pll to manage the clocks for other rtl logic.
Now the worst slack is reduced and logic level is 4 only.still timing violations are there.
it is showing within ip files. How can i add pipeline register here in this logics?
