Contributor
ContributorThis data path is too long, and its logic level is high:
You created a loop here which has increased the data delay, please consider inserting pipeline registers into this path in your design to reduce the logic level.
ContributorHi,
the critical path which you are showing is currently not available as i have added one pll to manage the clocks for other rtl logic.
Now the worst slack is reduced and logic level is 4 only.still timing violations are there.
it is showing within ip files. How can i add pipeline register here in this logics?
ContributorHi,
the critical path which you are showed in response is removed from timing violation as i added pll for managing clocks for rtl logic.
Now some other timing violations are there
these violations are within ddr3 library files. How to add pipeline register in this path?
ContributorHi,
Thanks for your response.
I just modified the qsys design for better timing performance so instead of ddr_pll clock , added pll ip to drive other rtl logic clock.
With that timing is improved. But still path has violation
The logic level is 4 only. These are listed for ddr3 ip library files. How to add pipeline register here?
