Forum Discussion
ContributorTiming constraints of Intel IPs
Super ContributorHi,
It seems the failure path is from the peripheral to the core.
You can open QSYS interconnect and check whether it is feasible to add a pipeline to the timing failing path. Please see the example below, as shown in the attachment.
Regards,
Richard Tan
anonimcs
@RichardTanSY_Altera wrote:Hi,
Please see the example below, as shown in the attachment.
Which attachment, and which example ?
And the failing path is from the IP to the interconnect, how am I supposed to add something inbetween ? It will end up with the same error as I'll connect the IP to another component in the Platform Designer for pipelining the failing signal...
- RichardT_altera
I just uploaded the attachment. I can say the system is not perfect when uploading attachment or images. Took a bit of time in between.
- anonimcs
I enabled all pipelines visible in "mm_interconnect_2" for both directions (Command and Response), and also tried optimizing the timing of the design by following these steps (https://www.intel.com/content/www/us/en/docs/programmable/683106/24-1-19-2-3/optimizing-timing.html) but the total slack of the failing paths are even worse than the ones in the screenshot I shared before.
