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anonimcs's avatar
anonimcs
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2 years ago

Timing constraints of Intel IPs

Hi all, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP co...
Memory
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


I have sent you an email with the steps to provide the project.


Regards,

Richard Tan


  • anonimcs's avatar
    anonimcs
    Icon for Contributor rankContributor
    2 years ago

    Hi @RichardTanSY_Altera ,

    I uploaded the project archive with the username you provided. Looking forward to your feedbacks.

    Thanks in advance