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anonimcs's avatar
anonimcs
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2 years ago

Timing constraints of Intel IPs

Hi all, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP co...
Memory
RichardT_altera's avatar
RichardT_altera
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2 years ago

I don't understand your first paragraph. Does the Quartus able to detect the sdc file? If the sdc is detected and added to the project, then the sdc does get generated.


Do you Locate Path and Not Locate Node? Seem to be you Locate Node the From Node.

Please confirm.


Perhaps you could share your .qar design (Project > Archive Project) so that I can investigate it further.


Regards,

Richard Tan


  • anonimcs's avatar
    anonimcs
    Icon for Contributor rankContributor
    2 years ago

    Hi @RichardTanSY_Altera ,

    This is what I meant by my first paragraph above. Please see the screenshot attached regarding the Timing Analyzer settings of the project. But it's my bad, when I expand the IP itself I can see the .sdc file added here.

    This is the path analysis in the Technology viewer after I ran the command locate [get_timing_paths -npaths 10] -tmv on the tcl console of the Timing Analyzer.

    For a Quartus archive, please send me an email with a link to upload the .qar file, the archive file is simply too large to add here.