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anonimcs's avatar
anonimcs
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2 years ago

Timing constraints of Intel IPs

Hi all, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP co...
Memory
RichardT_altera's avatar
RichardT_altera
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2 years ago

The sdc is automatically generated when you "Generate HDL" for the EMIF IP. You can search the .sdc files in the Project Navigator.

Or go to Assignment > Setting > Timing Analyzer > SDC Files to include in the project.

Quartus should detect and list out all the sdc file in the project.

Seems to me the failing path is from EMIF IP to the other part of design. Could you scroll your mouse to the failing path, Right-Click on it, Locate Path (failing path) in the Technology Map Viewer to confirm this is true?

Regards,

Richard Tan

anonimcs's avatar
anonimcs
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2 years ago

Hi,

In Assignment -> Setting -> Timing Analyzer I see the EMIF ip being added here (the .ip file), but not the generated .sdc file. I think (and hope) Quartus is detecting the generated .sdc and adding it here automatically, even though it doesn't show the generated .sdc files here.

For the failing path (I clicked on the one at the top in my previous screenshot), I do see the `tile_ctrl_inst` being highlighted in the Technology Map Viewer.