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MHahn4
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6 years ago

Timing Constraints for Cyclone 10GX PHY Interlaken

Hi, I'm trying to run the PHY transceivers on a Cyclone 10GX in Interlaken mode. While synthesising, there appears a "Timing requirements not met" critical warning. The problematic paths are for th...
MHahn4's avatar
MHahn4
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Yes. I've even tried a minimal design with loop back on the parallel data and only the three IP Cores (PHY, ATX-PLL, ResetController), but the timing errors still exist.