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Altera_Forum's avatar
Altera_Forum
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14 years ago

the waitrequest of avalon bus

Hi: the output shoud use the register many paper write that,but I find that if the waitrequest output with register will lead to delay a cycle.it is difficult to design the register timing.if use ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

But in some particular case,the waitrequest is not only controlled by the full,some other factors may lead to the data cann't be received by the slave,in other words even though the FIFO is not full,the waitrequest may need to pull up.

thank you!