Altera_ForumHonored Contributor14 years agoThe problem about setting up the FIFO's deep Hi guys, I have a big problem when I use the DCFIFO mega function. I need to store large amounts of data to achieve the data delay function. When I use the small FIFO(deep 1024),it works we...Show More
Altera_ForumHonored Contributor14 years agonot specifically, just make sure you have constraints on both clock domains.
Recent DiscussionsCyclone-V SCFIFO with M10K/MLAB memory - adding ECCAgilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wantedAgilex 7 slew rate reconfigurationSolvedAgilex-7 AXI MCDMA for PCIe hangConstraints not being picked for DCFIFO