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TGao
Occasional Contributor
Occasional ContributorThe difference of ALt_pll/Altera pll
Dear Sir/Madam, I'm porting projects from max10 to cyclone v, there're some difference in pll IP, as below, 1. the width of "phasecounterselect" are 3,but in cylone v, it's 5, difference? ...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
In Max 10,, you have Alt PLl and Cyclone V have altera pll.
Both PLL have different architectures,
To answer your question.
The register mapping of two devices are different.
Phasecounterslelect only 3 bits to select m or c couters
Refe Table :12 Max 10 user guide
In cyclone V Avalon bus is using for the reconfiguration on
For phase_en , signals are using in the Cyclone V devices not on Max 10, kindly find user guide [SR1] Table no: 6 for detailed explanation.
>> phase-step” equal to “scan_clk
Both are different ,refer page no: 58 of this document
