The DDR2 Controller with UniPHY has a port called "afi_reset". What causes this signal to assert? We are experiencing this signal asserting on a small subset of custom fpga boards. We are trying to debug the exact cause.

Dear SPols,

Thank you for joining this Intel Community.

The afi_reset signal will assert based on 2 conditions:

1. PHY is reset
2. PLL loses lock : This indicate that your afi_clk is not stable yet thus it will assert the reset signal until the PLL is locked.

For more details, you can refer to this user guide : https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/external-memory/emi_ddr3up_ug.pdf

Hope this helps

Regards,

NAli1