Stream-to-memory SGDMA does not write last QWord during a transfer

Problem solved.

SGDMA input port "in_empty[2:0]" came from a module where it was actually never assigned.

According to me, it should have been stuck to "000". BTW this is what it looked like into the waves.

but, for some reasons I still don't get, there was a side effect:

Here are the waves (http://img233.imageshack.us/img233/9348/bugma.png) before corrections:

http://img233.imageshack.us/img233/9348/bugma.png

And the waves (http://img845.imageshack.us/img845/7775/nobug.png) after correction:

http://img845.imageshack.us/img845/7775/nobug.png

These waves display signal signal m_write_byteenable_reg.

According to sgdma.vhd, line 1946, this signal only depends on signals sink_stream_empty and shifti:

m_write_byteenable_reg <= A_EXT(    (
                                        (
                                            (
                                                (
                                                    (
                                                        (
                                                            (
                                                                   (A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000111"))), (std_logic_vector'("000000000000000000000000") & (shift7)), std_logic_vector'("00000000000000000000000000000000")))
                                                                OR (A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000110"))), (std_logic_vector'("000000000000000000000000") & (shift6)), std_logic_vector'("00000000000000000000000000000000")))
                                                            )
                                                            OR     (A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000101"))), (std_logic_vector'("000000000000000000000000") & (shift5)), std_logic_vector'("00000000000000000000000000000000")))
                                                        )
                                                        OR         (A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000100"))), (std_logic_vector'("000000000000000000000000") & (shift4)), std_logic_vector'("00000000000000000000000000000000")))
                                                    )
                                                    OR             (A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000011"))), (std_logic_vector'("000000000000000000000000") & (shift3)), std_logic_vector'("00000000000000000000000000000000")))
                                                )
                                                OR                 (A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000010"))), (std_logic_vector'("000000000000000000000000") & (shift2)), std_logic_vector'("00000000000000000000000000000000")))
                                            )
                                            OR                     (A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000001"))), (std_logic_vector'("000000000000000000000000") & (shift1)), std_logic_vector'("00000000000000000000000000000000")))
                                        )
                                        OR                         (A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000000"))), (std_logic_vector'("000000000000000000000000") & (shift0)), std_logic_vector'("00000000000000000000000000000000")))
                                    ),
                                8);

code is ugly, but it corresponds to:

if (sink_stream_empty = "000") then
    m_write_byteenable_reg <= "11111111";
if (sink_stream_empty = "001") then
    m_write_byteenable_reg <= "01111111";
if (sink_stream_empty = "010") then
    m_write_byteenable_reg <= "00111111";
if (sink_stream_empty = "011") then
    m_write_byteenable_reg <= "00011111";
if (sink_stream_empty = "100") then
    m_write_byteenable_reg <= "00001111";
if (sink_stream_empty = "101") then
    m_write_byteenable_reg <= "00000111";
if (sink_stream_empty = "110") then
    m_write_byteenable_reg <= "00000011";
else
    m_write_byteenable_reg <= "00000001";
end if;

For some reasons, shifti signals are not correctly displayed (wrong values and signal name in red), but still according to sgdma.vhd, lines 1931 to 1952:

all_one <= std_logic_vector'("11111111");
shift7 <= Std_Logic_Vector'(std_logic_vector'("0000000") & A_ToStdLogicVector(all_one(0)));
shift6 <= Std_Logic_Vector'(std_logic_vector'("000000") & all_one(1 DOWNTO 0));
shift5 <= Std_Logic_Vector'(std_logic_vector'("00000") & all_one(2 DOWNTO 0));
shift4 <= Std_Logic_Vector'(std_logic_vector'("0000") & all_one(3 DOWNTO 0));
shift3 <= Std_Logic_Vector'(std_logic_vector'("000") & all_one(4 DOWNTO 0));
shift2 <= Std_Logic_Vector'(std_logic_vector'("00") & all_one(5 DOWNTO 0));
shift1 <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & all_one(6 DOWNTO 0));
shift0 <= all_one;

shift0 = "11111111",

shift1 = "01111111",

shift2 = "00111111",

...

shift7 = "00000001",

So I don't understand why m_write_byteenable_reg signal behaves differently since in both cases signlas in it equation behave the same...

m_write_byteenable_reg = "00000000" is only possible if the following conditions are all false:

(std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000111")
(std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000110")
(std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000101")
(std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000100")
(std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000011")
(std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000010")
(std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000001")
(std_logic_vector'("00000000000000000000000000000") & (sink_stream_empty)) = std_logic_vector'("00000000000000000000000000000000")

which I don't think is possible...

Has anyone any idea about that?

- Julien