Stratix4 PCIE endpoint Hard IP and Avalon ST

Thanks BrettFavre for pointing that out. What I don’t get is why such an important deviation of the Avalon ST protocol is not explained in more detail in the PCIe Compiler User Guide. Don’t want to know how many developers already spent hours searching for the bug in her IP finding only the cryptic explanation of the signal. To an uninitiated, it looks more like a description of the AST readLatency property than a red colored note about a major deviation from the AST protocol.

In addition, the restriction doesn’t make sense at all: The AST adaptor has to buffer the frame anyway for being able to handle tx_st_err<n> properly. Allowing stop-and-go DW indication could avoid the additional buffering now required for any application not able to drive the data stream at full rate. A generic approach is to place a Fifo in front of the AST Tx I/F that forwards a frame only if it was finished by the actual sender. This accounts to higher latency, more IP, more bugs, more memory, more power dissipation, for no good reason.

Maybe – hopefully! – Altera will redesign their AST adaptor to allow tx_st_valid to be driven arbitrarily, so this restriction can go away someday.