Stratix10 P-Tile PCIe Hot Reset

Hi anat,

My apology for the delayed response.

You can read the Bridge Control Register bit location 6, Secondary Bus Reset register, to obtain the information on hot reset on the host side. Alternatively, you can enable the Hard IP Reconfiguration interface when configuring the PCIe device in Endpoint mode, and obtain the hot reset information via this interface from the FPGA side.

You may refer to the documents:

1. PCIe Base Specification Rev. 4.0 Section 7.5.1.3.13 Bridge Control Register: http://www.pcisig.com/

2. P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683059/24-3/hard-ip-reconfiguration-interface.html

I hope this helps.

Thanks.

Best Regards,

Ven

*Kindly take note that 31 Mar and 1 Apr 2025 are national public holidays, please expect a delay in response.