Hmm .. you're using the Stratix V PCIe kit. The clock I'm referring to is not the PCIe System clock thats on the system (PC), but rather on the FPGA Board. All FPGA boards have a xtal oscillator or programmable oscillator which feeds the clock into the FPGA chip. If this refclk is not connected to the correct input refclk pin for the design, the PLL will not get its input clock and will never lock on.
This FPGA refclk can also be dirty at times due to other factors. You need to check
- Refclk input to FPGA is routed to correct pin in the FPGA and design.
- This same refclk is the one thats connected as input to PLL
- PLL in the design is configured and generated correct.
New Contributor
