Stratix V pcie refclk lock problem

If you're having trouble getting the PLL to lock in the design I suggest taking a look at the input clock waveform. Check if the input clock is mapped to the correct pin that is connected to the REFCLK in the PLL and also capture the clock to check if the edges are okay and that there's not much jitter etc. If the input clock is very dirty, the PLL will not be able to lock onto it and generate the requested output clocks.