Stratix 10M PCIe BAR0 size incorrect

Update:

I added a Avalon-MM Pipeline Bridge to the Qsys system and exported its master interface instead, and now the "region size" exported from lspci looks correct.

However, I'm still getting bus errors + driver failure if I write more than 16B to BAR0. Can someone tell me if my overall approach is correct?

1. Setup link to FPGA endpoint using uio_pci_generic
2. Open the file handle at /sys/class/uio/uio0/device/resource0 (I know that this is the correct one). The permissions to the open() call are O_RDWR | O_SYNC.
3. mmap the file handle returned from step #2. The protection args given to mmap are PROT_READ | PROT_WRITE, and the flag is MAP_SHARED.
4. memset N bytes to the pointer returned from step #3.
5. msync the pointer returned from step #3.
6. Read the pointer returned from step #3 32-bits at a time.

It's after step #6 that things start to act weirdly if I try to access more than 16B.