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roeekalinsky's avatar
roeekalinsky
Icon for Contributor rankContributor
4 years ago

Stratix 10 UCID IP bug: partition conflict

If the S10 UCID IP is used and its clock input comes from a sector clock gate, Quartus errors out during the fitter stage with the following message: Error (19732): Sector clock gate s10clkctrl_ip_...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Yes, the error is indicating that the clock is in different logical partitions and thus quartus is not able to fit the design. What i am suggesting is selecting different CLK input from the pin planner.


I have tried to duplicate the design by connecting the Clock Control IP's output to S10 Chip ID, no issue on it.


  • roeekalinsky's avatar
    roeekalinsky
    Icon for Contributor rankContributor
    4 years ago
    @YuanLi_S_Intel wrote:

    Yes, the error is indicating that the clock is in different logical partitions and thus quartus is not able to fit the design. What i am suggesting is selecting different CLK input from the pin planner.

    My experimentation didn't show any dependence on pin location. Only the logical partition problem, which seems to be independent of physical location.

    @YuanLi_S_Intel wrote:

    I have tried to duplicate the design by connecting the Clock Control IP's output to S10 Chip ID, no issue on it.

    Can you please post your design files, so I can see what's different from mine?

    Thanks,
    -Roee