Contributor
Regular ContributorFrom the error messages, it seems like the clock input cannot be fitted. Can you change another clock source?
Contributor
@YuanLi_S_Intel wrote:
From the error messages, it seems like the clock input cannot be fitted.
The error message doesn't indicate that there is any physical or architectural reason why it can't be fitted. The problem it's complaining about is the different logical partitions, which Quartus itself created earlier in the flow.
@YuanLi_S_Intel wrote:
Can you change another clock source?
That's beside the point, but to answer your question: In my real world design where this issue came up, suffice it to say there are good reasons why I'm using sector clock gating. Yes, I could potentially work around this issue by changing the clocking scheme, but it would come at a cost of increased resource utilization and power consumption and reduced attainable timing performance. That's undesirable.
I'm not looking to you to suggest design alternatives. I'm looking to you to please directly address the apparent self-inflicted incompatibility in Quartus between the Stratix 10 chip ID IP and sector clock gating.
Thanks,
-Roee
