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Smarty's avatar
Smarty
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Stratix 10 reset_status asserted after FPGA is totally configured ?

The Stratix 10 Avalon Streaming Interface for PCI Express User Guide provides informations about the reset_status output of the HIP core. Is it safe to assume, that reset_status is deasserted (rese...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    4 years ago

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SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Yes, you are right.