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Smarty's avatar
Smarty
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Stratix 10 reset_status asserted after FPGA is totally configured ?

The Stratix 10 Avalon Streaming Interface for PCI Express User Guide provides informations about the reset_status output of the HIP core. Is it safe to assume, that reset_status is deasserted (rese...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

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SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Yes, it is safe to use the reset_status for the AVMM or AVST interface. You can refer to the reset connection from the IP-generated example design. From the example design, it enabled the Avalone-ST reset output port (same function as reset_status) to connect with the reset of the on-chip memory and application interface.



  • Smarty's avatar
    Smarty
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    I realized, that I was using an old version of the user guide (2019.09.30). After looking into the latest version I found that there is now a new input called ninit_done.

    Is it correct that this input cannot be tied to '0' but is required to be connected to the reset release IP ?

    Thanks