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Smarty's avatar
Smarty
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5 years ago
Solved

Stratix 10 reset_status asserted after FPGA is totally configured ?

The Stratix 10 Avalon Streaming Interface for PCI Express User Guide provides informations about the reset_status output of the HIP core. Is it safe to assume, that reset_status is deasserted (rese...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

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SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

At the initial power-up, you may use the nint_done signal together to hold the core logic in reset before entering the user mode. The reset_status will be helpful when you reboot the host or issue a perst from the host or trigger the npor, while the FPGA image is still alive, and that signal can use to reset your application logic.



  • Smarty's avatar
    Smarty
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thanks for the additional informations.

    I think I haven't provided the whole picture, so I am trying once again:

    Due to the nature of the S10 architecture the safest approach is to reset the user logic with the reset release ip output after the FPGA is completely configured.

    Problem is, that we can't route the nint_done output of the reset release IP to the Avalon streaming masters / slaves that communicate with the S10 PCIe HardIP .

    According to the UG on page 80 of the HIP with streaming interfaces, there is the statement that reset_status can be used to reset the user logic. This seems to solve the problem for us, since those avalon streaming slaves/masters can now be reset with reset_status und the other parts of the FPGA with the reset release IP output.

    Is this a safe approach ?