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Smarty's avatar
Smarty
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Stratix 10 reset_status asserted after FPGA is totally configured ?

The Stratix 10 Avalon Streaming Interface for PCI Express User Guide provides informations about the reset_status output of the HIP core. Is it safe to assume, that reset_status is deasserted (rese...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

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SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


The application layer can monitor this signal to determine when the IP core has come out of reset. This is not a concern for the application layer can't detect this signal during the initial power-up. The application layer should also monitor the tx_st_ready signal to determine when the transaction layer is ready to accept data.


Regards -SK




  • Smarty's avatar
    Smarty
    Icon for New Contributor rankNew Contributor
    5 years ago

    The thing that concerns me, is the case where the HIP is configured in autonomous mode.

    In this case the HIP comes surely out of reset before the FPGA fabric. Now it is important to know,

    how "comes out of reset" is defined. In other words, the question is : Is it safe to use reset_status in this operation mode as high active reset for the user logic ? Is it safe to assume, that user logic will see reset_status = 1 and reset ?