Forum Discussion
LennartVH
New Contributor
New ContributorStratix 10 M20K Clock Clock Enable for ECC Pipeline register
Hi there, In the M20K documentation on ECC, there is mention of an optional pipeline register within the ECC pipeline for achieving higher FMax. It is not entirely clear if adding a clock enable ...
In the end I was able to test that yes indeed, applying a clock enable to the output registers does add a clock enable to the pipeline registers as well.
As for the other questions, they're still a mystery, but at least we can continue development with this.
LennartVHNew Contributor
New ContributorHi SyafieqS,
Thank you for your time. This is still an open question for us. As our build system is broken right now I can't test it myself, so having confirmation on how the M20K output registers work would really help.
Kind regards,
Lennart
