Stratix 10 E-TILE reference clock

Hi Mikhail,

I have clarified with Intel internal team.

Unfortunately E-tile refclk doesn't support direct connection to FPGA core logic as I suspected earlier.

• This is a explanation mistake in S10 pin connection guide doc. We will fix and update the doc accordingly

My recommendation is as below

1. If you insist of using E-tile refclk then you can choose to configure E-tile NativePHY in PLL mode where it convert one of E-tile transceiver channel into PLL that can be used to clock FPGA core logic. Refer to chapter 2.2.11 PLL mode

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_etile_xcvr_phy.pdf#page=63&zoom=100,0,0

1. Else you can also use any IOPLL refclk pin or any IOPLL output clock to clock FPGA core logic

Thanks.

Regards,

dlim