Stratix 10 DX Hardened UPI & PCIe 4.0 IP Documentation

Question

Where can I find get access to datasheets and app notes for Stratix 10 DX UPI and PCIe 4.0 hardened IPs ?

I got Stratix 10DX Development kit which has 3UPI links for connection to Xeon CPU and expected to evaluate UPI interconnect with Xeon Gold and Platinum Gen4 CPUs for latency critical design.

But cannot find neither datasheets & app notes as well as any sample design for CPU-FPGA data exchange over UPI.

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-dx.html

Best regards,

Sam

wincent_altera · Answer

Hi,You can get the design and user guide viaRegards,Wincent_Intel

samwinw · Answer

Wincent,I couldn't see the link or document you've tried to attach to your responseRegards,Sam

wincent_altera · Answer

Hi,You can get the user guide and design example via the link you provided earlyhttps://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-dx.htmlFor the user guide User GuideDesign exampleES (19.3 or higher)Production (19.3 or higher)Regards,Wincent_Intel

samwinw · Answer

Wincent,there are no UPI example in examples folder from installation for the Stratix 10 DX Dev Kit.And UPI hardened IP documentation either.

wincent_altera · Answer

Hi,I check with internal, this IP and design is hidden IP.Can you please check with Distributor FAE/ Intel Sales team , They might able to provide you the example with better business justification.Regards,Wincent_Intel

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Stratix 10 DX Hardened UPI & PCIe 4.0 IP Documentation

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