Startix10GX device PIPE Native phy IP showing error channel misplacement error

Hi,

I'm using Stratix10GX fpga devkit and generated PIPE Native phy IP throwing placement error as follows on Quartus17.1IR2.

any body have any ideas on how to fix this placement issue?

This may relates to quartus rule check I guess, since I see almost similar error on every experiment.

Thanks

Satish

------------------------------Error(19376): PIPE master channel < txp[2](n) > has to be placed at second or fifth location of the HSSI tile. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_PMA_TX_CGB(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error(175001): The Fitter cannot place 1 HSSI_PMA_TX_CGB, which is within Stratix 10 L-Tile ES1 Transceiver Native PHY s10_phy_pipex4_altera_xcvr_native_s10_16930_ws3np3i.

Info(14596): Information about the failing component(s):

Info(175028): The HSSI_PMA_TX_CGB name(s): altera_phy|xcvr_native_s10_0|g_xcvr_native_insts[2].ct1_xcvr_native_inst|ct1_xcvr_native_inst|inst_ct1_xcvr_channel|gen_ct1_hssi_pma_tx_cgb.inst_ct1_hssi_pma_tx_cgb

Error(16234): No legal location could be found out of 95 considered location(s). Reasons why each location could not be used are summarized below:

Error(175006): Could not find path between the HSSI_PMA_TX_CGB and destination HSSI_CR_PMA_TX_BUF

Info(175027): Destination: HSSI_CR_PMA_TX_BUF altera_phy|xcvr_native_s10_0|g_xcvr_native_insts[2].ct1_xcvr_native_inst|ct1_xcvr_native_inst|inst_ct1_xcvr_channel|gen_ct1_hssi_cr_pma_tx_buf.inst_ct1_hssi_cr_pma_tx_buf

Error(175022): The HSSI_PMA_TX_CGB could not be placed in any location to satisfy its connectivity requirements

Info(175021): The HSSI_CR_PMA_TX_BUF was placed in location HSSICRPMATXBUF_1C2

Info(175029): 93 locations affected

Info(175029): HSSIPMATXCGB_1C3

Info(175029): HSSIPMATXCGB_1C4

Info(175029): HSSIPMATXCGB_1C5

Info(175029): HSSIPMATXCGB_1D0

Info(175029): HSSIPMATXCGB_1D1

Info(175029): HSSIPMATXCGB_1D2

Info(175029): HSSIPMATXCGB_1D3

Info(175029): HSSIPMATXCGB_1D4

Info(175029): HSSIPMATXCGB_1D5

Info(175029): HSSIPMATXCGB_1E0

Info(175029): HSSIPMATXCGB_1E1

Info(175029): HSSIPMATXCGB_1E2

Info(175029): and 81 more locations not displayed

Error(175003): The HSSI_PMA_TX_CGB location is occupied (2 locations affected)

Info(175029): HSSIPMATXCGB_1C0. Already placed at this location: HSSI_PMA_TX_CGB altera_phy|xcvr_native_s10_0|g_xcvr_native_insts[0].ct1_xcvr_native_inst|ct1_xcvr_native_inst|inst_ct1_xcvr_channel|gen_ct1_hssi_pma_tx_cgb.inst_ct1_hssi_pma_tx_cgb

Info(175029): HSSIPMATXCGB_1C1. Already placed at this location: HSSI_PMA_TX_CGB altera_phy|xcvr_native_s10_0|g_xcvr_native_insts[1].ct1_xcvr_native_inst|ct1_xcvr_native_inst|inst_ct1_xcvr_channel|gen_ct1_hssi_pma_tx_cgb.inst_ct1_hssi_pma_tx_cgb

Error(15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.

Error(16297): An error has occurred while trying to initialize the plan stage.

Error: Quartus Prime Beta Fitter was unsuccessful. 10 errors, 1 warning

Error: Peak virtual memory: 11208 megabytes

Error: Processing ended: Tue Jul 18 11:58:08 2017

Error: Elapsed time: 00:03:44

Error: Total CPU time (on all processors): 00:01:49

Error(293001): Quartus Prime Beta Full Compilation was unsuccessful. 11 errors, 1 warning