SRAM -> Frame Reader -> 2D FIR Filter -> SRAM

Ahh, and I get a lot of warnings related to the frame reader during the sopc generation process. But I dont have a clue why...

Warning: Warning (10238): Verilog Module Declaration warning at alt_vipvfr110_prc_read_master.v(47): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "alt_vipvfr110_prc_read_master"
Warning: Warning (10236): Verilog HDL Implicit Net warning at alt_vipvfr110_prc.v(142): created implicit net for "master_clock"
Warning: Warning (10236): Verilog HDL Implicit Net warning at alt_vipvfr110_prc.v(143): created implicit net for "master_reset"
Warning: Warning (10445): VHDL Subtype or Type Declaration warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(178): subtype or type has null range
Warning: Warning (10445): VHDL Subtype or Type Declaration warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(181): subtype or type has null range
Warning: Warning (10445): VHDL Subtype or Type Declaration warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(261): subtype or type has null range
Warning: Warning (10445): VHDL Subtype or Type Declaration warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(262): subtype or type has null range
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(178): object "wdata_fifo_wrusedw" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(179): object "wdata_fifo_full" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(180): object "wdata_fifo_almost_full" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(182): object "wdata_fifo_empty" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(183): object "wdata_fifo_almost_empty" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(184): object "wdata_fifo_wrreq" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(185): object "wdata_fifo_data" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(186): object "wdata_fifo_rdreq" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(187): object "wdata_fifo_q" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(189): object "wdata_fifo_empty_next" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(193): object "rdata_fifo_full" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(194): object "rdata_fifo_almost_full" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(195): object "rdata_fifo_rdusedw" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(197): object "rdata_fifo_almost_empty" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(212): object "cmd_fifo_wrusedw" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(214): object "cmd_fifo_almost_full" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(215): object "cmd_fifo_rdusedw" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(217): object "cmd_fifo_almost_empty" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(229): object "writing" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(229): object "reading" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(239): object "wdata_en" assigned a value but never read
Warning: Warning (10541): VHDL Signal Declaration warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(260): used implicit default value for signal "byte_enable_next" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning: Warning (10296): VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(424): ignored assignment of value to null range
Warning: Warning (10296): VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(425): ignored assignment of value to null range
Warning: Warning (10296): VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(437): ignored assignment of value to null range
Warning: Warning (10631): VHDL Process Statement warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(641): inferring latch(es) for signal or variable "byte_enable", which holds its previous value in one or more paths through the process
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_general_fifo.vhd(230): object "ram_fifo_empty" assigned a value but never read
Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_ram_fifo.vhd(129): object "port_a_q" assigned a value but never read
Warning: Warning (10240): Verilog HDL Always Construct warning at alt_vipvfr110_common_avalon_mm_slave.v(45): inferring latch(es) for variable "interrupt_register", which holds its previous value in one or more paths through the always construct
Warning: Warning (10230): Verilog HDL assignment warning at alt_vipvfr110_common_avalon_mm_slave.v(72): truncated value with size 35 to match size of target (32)
Warning: Warning (10240): Verilog HDL Always Construct warning at alt_vipvfr110_common_avalon_mm_slave.v(45): inferring latch(es) for variable "interrupt_register", which holds its previous value in one or more paths through the always construct
Warning: Warning (10230): Verilog HDL assignment warning at alt_vipvfr110_common_avalon_mm_slave.v(72): truncated value with size 49 to match size of target (32)
Warning: Warning (10240): Verilog HDL Always Construct warning at alt_vipvfr110_vfr_control_packet_encoder.v(62): inferring latch(es) for variable "control_data", which holds its previous value in one or more paths through the always construct
Warning: Warning (10230): Verilog HDL assignment warning at alt_vipvfr110_vfr_control_packet_encoder.v(82): truncated value with size 32 to match size of target (4)