SPI Core: Strange problem with sample and shift clocks

Hi, FvM, thanks for the reply :-)

I'm using the serial peripheral interface - master / slave (http://www.cast-inc.com/ip-cores/interfaces/spi_ms/cast_spi_ms-a.pdf) IP core

that comes with Qsys. I have one board with a Master instance of

that core, communicating with another board with a Slave Instance.

I'll try checking the clock constraints, but I'm not very hopeful: I have

a NiosII with a TSE core in the same system, and they are working fine. Why should the SPI (which is rather slow) cause timing issues?

I also tried inserting a 1 us delay between the SS_N and SCLK in the SPI master, but that didn't work either.

Thanks,

Ran