Forum Discussion

New Contributor

6 years ago

Specifying timing relative to EMIF pll reference clock

Hello all, I am using an Arria 10 10AX027H4F35E3SG and have included a DDR4 EMIF. I am feeding the FPGA a 133MHz clock as the pll reference. This same clock is used for all the board interface tim...

WKapp

New Contributor

6 years ago

NAli1, Thank you for the reply. I had pretty much figured out there was no solution for this situation. I am surprised the designers of the IP did not consider this situation and accommodate it. Oh well, can’t change it now☹. Unfortunately, I cannot use afi_clk externally as this FPGA is not the source of the board clock. There are many other FPGAs and external logic that all must be clocked in phase. Thanks, Bill