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WKapp's avatar
WKapp
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6 years ago

Specifying timing relative to EMIF pll reference clock

Hello all, I am using an Arria 10 10AX027H4F35E3SG and have included a DDR4 EMIF. I am feeding the FPGA a 133MHz clock as the pll reference. This same clock is used for all the board interface tim...
NurAida_A_Intel's avatar
NurAida_A_Intel
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6 years ago

Hi WKapp,

I consult timing expert guy, and he also aware about the difficultly in meeting timing based on your situation as the clock is not in the same phase.

His recommendation for you is to connect the afi_clk out externally to your External FF instead of using clock distribution so that all the clock will have same source be in same phase.

I attached diagram for your reference.

Hope this helps.

Thanks

Regards,

NAli1

  • WKapp's avatar
    WKapp
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    6 years ago
    NAli1, Thank you for the reply. I had pretty much figured out there was no solution for this situation. I am surprised the designers of the IP did not consider this situation and accommodate it. Oh well, can’t change it now☹. Unfortunately, I cannot use afi_clk externally as this FPGA is not the source of the board clock. There are many other FPGAs and external logic that all must be clocked in phase. Thanks, Bill
    • NurAida_A_Intel's avatar
      NurAida_A_Intel
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      6 years ago

      Dear WKapp,

      Understand the pain that you are facing. I sincerely apologize for the inconvenience caused.

      Regards,

      NAli1

    • WKapp's avatar
      WKapp
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      6 years ago
      No need to apologize. Thanks for helping. Bill