Source of errors in data from SGDMA

Hello,

Using the example in the excellent document in this thread (http://www.alteraforum.com/forum/showthread.php?t=1269&page=2) I wrote a short SDC file and recompiled my project. After removing the phase shift on the PLL to meet the timing requirements the new constrained project works perfectly with no errors on the burst reads & writes, running at 70Mhz, so problem solved! :D

Thank you very much Daixiwen. I really appreciate all your time you've spent helping me with this.

I'll get another SDC written up for the LCD project and then hopefully everything should work from here on in.

If I may just ask one last thing about the timing constraints; when I set my PLL to output 70MHz I get a couple of reported failures on the PLL output which feeds the memory clock pin (the one that I originally had the phase shift on).

I just wanted to know what the source of this was, I was thinking it had something to do with the phase of this clock with respect to the controller logic but when I try to offset it with a phase shift in the PLL it makes the slack worse.

I remove the PLL phase shift in order for the timing analysis to pass, so I assume the phase shift (if needed) is being applied automatically based on my timing constraints?

Thank you again!

Sebastian