Honored Contributor
Honored ContributorI will look at the timing parameters in the controller again but ive checked them three times now. The data sheet gives me a bit of trouble as its not as verbose as an equivalent from a company like Hynix.
The SDRAM I am using is a K4S510832M (attached). The controller settings are: Data: 8 Chip Select: 1 Banks: 4 Addr. Width: 13 Col. Width: 11 I would suppose these have to be correct or else even the simple memory tests would not pass. CAS Latency: 3 Data Sheet specifies CL of 2 & 3. Init. Refresh. Cycles: 2 Cannot find specification in data sheet Issue one refresh command every: 15.625 us Data sheet specifices refresh period of 64ms/8K cycles which is what I used to calculate this. Delay after powerup, before initialization: 100us Cannot find specification in data sheet Duration of refresh command (t_rfc): 70ns Cannot find specification in data sheet Duration of precharge command (t_rp): 20ns Cannot find specification in data sheet ACTIVE to READ or WRITE delay (t_rcd): 20ns Data sheet specifies tRCD but as the !RAS to !CAS delay which I don't think means the same thing Access time (t_ac): 5.5ns Data sheet specifies 'Clock to output valid delay' as the closest thing I could find. Write recovery time (t_wr): 14ns Cannot find specification in data sheet Im thinking the memory does power up and work with no bursts, so the initialization, refresh and precharge commands are likely OK. So I should tweak the t_rcd, t_ac and t_wr values increasing them a few times to see what effect that has (assuming that the memory is sampling too quickly resulting in dropped data and misplaced bytes).
