Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi Daixiwen,
It does appear to be the burst accesses. I have my program write a set value to every memory address in one go, then attempt to read the entire memory back checking the content of each address against this value. If I choose a value such as 0x0, 0xF0F0F0F0 or 0xFFFFFFFF it passes fine, however if I provide the program with a 'random' integer such as 468177612 it fails on every address, but not just on reading back any value. For the value above the program will read, from every address, 454813650. There may be one or two odd values in the list but for over 4000 addresses it will fail with that specific value. (My data cache is 1Kbyte and the line size is 32bytes) A similar pattern emerges when I provide other values; using uncached accesses makes no difference. The example memory test program doesnt get past the first bit of the data bus. If I disable the data cache of the NIOS the program completes successfully regardless of the values provided. Surely this means the error is with my SDRAM controller. I have tried manually tuning the PLL, so unless I have the timing parameters wrong does this mean I have a hardware problem?